A Modified Design of Test Pattern Generator for Built-In-Self- Test Applications

Test Pattern Generators (TPG) are very important logic part of the Circuits that have self-test features. Nowadays, the self-test feature is an in-built part of the modern application hardware designs. This feature enables the user to test and verify the specific hardware failure with the help of the hardware itself. To enable self-test an extra operational and control circuit is required by the application based operational and control circuit. The size of the self-test block is generally small as compared to the actual hardware. Most of the self-test hardware includes Linear Feedback Shift Register (LFSR) to generate the test signal pattern in the self-test mode of circuit operation. In the present work a simple 3-FF based modified design of TPG is designed and simulated to generate a 4-bit test signal sequence. The present work also shows FPGA based simulation and synthesis of a 16-bit TPG design using the 4-bit TPG. The present TPG design concept can be replicated to generate a test sequence of higher bit length for advanced applications. The present design is simulated on Xilinx tool for functional verification.